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ds07-13742-1e fujitsu semiconductor data sheet copyright?2006 fujitsu li mited all rights reserved ?check sheet? is seen at the following support page url : http://jp.fujitsu.com/microelectr onics/products/micom/support/index.html ?check sheet? lists the minimal require ment items to be checked to prevent problems beforehand in system development. be sure to refer to the ?check sheet? for the latest cautions on development. 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90980 series mb90982/mb90f983/MB90V485B description the mb90980 series is a 16-bit general-purpose fujitsu microcontroller designed for process control in con- sumer devices and other applications re quiring high-speed real-time processing. the f 2 mc-16lx cpu core instruction set retains the at architecture of the f 2 mc* 1 family, with additional instruc- tions for high-level languages, expanded addressing mode, enhanced multiply-drive instructions, and complete bit processing. in addition, a 32-bit accumulato r is provided to enable long-word processing. the mb90980 series features embedded peripheral resource s including 8/16-bit ppg, expanded i/o serial inter- face, uart, 10-bit a/d converter, 16-bit i/o timer, 8/16-bit up/down-counter, pwc timer, i 2 c* 2 interface, dtp/ external interrupt, chip select, and 16-bit reload timer. *1 : f 2 mc is the abbreviation of fujitsu flexible microcontroller. *2 : purchase of fujitsu i 2 c components conveys a license under the philips i 2 c patent rights to use, these components in an i 2 c system provided that the system conforms to the i 2 c standard specification as defined by philips. features clock ? minimum instruction execution time: 40.0 ns/6.25 mhz base frequency multiplied 4 (25 mhz internal operating frequency/3.3 v 0.3 v) 62.5 ns/4 mhz base frequency multiplied 4 (16 mhz internal operating frequency/3.0 v 0.3 v) pll clock multiplier (continued)
mb90980 series 2 (continued) maximum memory space ? 16 mbytes instruction set optimized for controller applications ? supported data types (bit, byte, word, or long word) ? typical addressing modes (23 types) ? enhanced signed multiplication/division in struction and reti instruction functions ? 32-bit accumulator for enhanced high-precision calculation instruction set designed for high-level language (c) and multi-task operations ? system stack pointer adopted ? instruction set compatibility and barrel shift instructions enhanced execution speed ? 4 byte instruction queue enhanced interrupt functions ? 8 levels setting with programmable priority, 8 external interrupt pins data transmission function ( dmac) ? up to 16 channels embedded rom ? flash versions : 192 kbytes, mask versions : 128 kbytes embedded ram ? flash versions : 12 kbytes, mask versions : 10 kbytes general purpose ports ? up to 48 ports (10 ports with output open-drain settings) 8/10-bit a/d converter ? 8-channel rc sequential comparison type (10-bit resolution, 3.68 s conversion time (at 25 mhz) ) i 2 c interface ? 1 channel, p76/p77 n-ch open drain pin (without p-ch) uart ? 1 channel extended i/o serial interface (sio) ? 2 channels 8/16-bit ppg ? 2 channels (with 8-bit 4 channels/16-bit 2 channels mode switching function) 8/16-bit up/down timer ? 1 channel (with 8-bit 2 channels/16-bit 1-channel mode switching function) 16-bit pwc ? 2 channels (capable of compare the inputs) 16-bit reload timer ? 1 channel 16-bit i/o timer ? 2 channels input capture, 4 channels output compare, 1 channel free run timer on chip dual clock generator system low-power consumption (standby) mode ? with stop mode, sleep mode, cpu intermittent op eration mode, watch timer mode, timebase timer mode
mb90980 series 3 packages ? lqfp 64 process ? cmos technology power supply voltage 3 v, single source (some ports can be operated by 5 v power supply.)
mb90980 series 4 product lineup (continued) item part number mb90982 mb90f983 MB90V485B classification mask rom product flash memory product evaluation product rom size 128 kbytes 192 kbytes ? ram size 10 kbytes 12 kbytes 16 kbytes cpu function number of instructions : 351 instruction bit length : 8-bit, 16-bit instruction length : 1 byte to 7 bytes data bit length : 1-bit, 8-bits, 16-bits minimum execution time : 40 ns (25 mhz machine clock) ports general-purpose i/o ports: up to 48 general-purpose i/o ports (cmos output) general-purpose i/o ports (w ith pull-up resistance input) general-purpose i/o ports (n-ch open drain output) uart 1 channel, start-stop synchronized 8/16-bit ppg 8-bit 4 channels/16-bit 2 channels 8-bit 6 channels/ 16-bit 3 channels 8/16-bit up/down counter/timer 6 event input pins, 8-bit up/down counters : 2 8-bit reload/compare registers : 2 16-bit i/o timers 16-bit free run timer number of channels : 1 overflow interrupt output compare (ocu) number of channels : 4 pin input factor : a match signal of compare register number of channels : 6 pin input factor : a match signal of compare register input capture (icu) number of channels : 2 rewriting a register value upon a pin input (rising, falling, or both edges) dtp/external interrupt circuit number of external interrupt channels : 8 (edge or level detection) extended i/o serial interface 2 channels, embedded i 2 c interface* 2 1 channel pwc 2 channels 3 channels timebase timer 18-bit counter interrupt cycles: 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 mhz base oscillator) a/d converter conversion resolution : 8/10-bit, switchable one-shot conversion mode (converts selected channel 1 time only) scan conversion mode (conversion of multiple consecutive channels, programmable up to 8 channels) continuous conversion mode (repeated conversion of selected channels) stop conversion mode (conversion of selected channels with repeated pause) watchdog timer reset generation interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (minimum value, at 4 mhz base oscillator) low-power consumption (standby) modes sleep mode, stop mode, cpu intermittent mode, watch timer mode, timebase timer mode process cmos type flash model 3v/5v power supply* 1 mask model 3v/5v power supply* 1 3v/5v power supply* 1 emulator power supply* 3 ?? yes
mb90980 series 5 (continued) *1 : 3v/5v i/f pin : all pins should be for 3 v power supply without p24 to p27, p30 to p37, p40 to p42, p70 to p74, p76, and p77. *2 : p76/p77 pins are n-ch open drai n pins (without p-ch) at built-in i 2 c. *3 : it is setting of jumper switch (t ool vcc) when emulator (mb2147-01) is used. please refer to the hardware manual of mb2147-01 or mb2147-20 (?3.3 emulator-dedicated power supply switching?) about details. note : ensure that you must write to flash at v cc = 3.13 v to 3.60 v (3.3 v + 10 % , ? 5 % ) .
mb90980 series 6 pin assignment (top view) (fpt-64p-m03) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v ss x1 x0 mod2 mod1 mod0 p84/irq4 p85/irq5 p86/irq6 p87/irq7 p90/sin1 p91/sot1 p92/sck1 p93/frck/adt g p96/in0 v ss 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 av cc avrh p27/ppg3 p26/ppg2 p25/ppg1 p24/ppg0 p 37/pwc1 p 36/pwc0 p35/zin1 p34/bin1 p33/ain1 p32/zin0 p31/bin0 p30/ain0 p42/sck2 v cc 5 v ss p 41/sot2 p40/sin2 p77/sda p76/scl p74/tot0 p73/tin0 p 72/sck0 p 71/sot0 p70/sin0 p a3/out3 p a2/out2 p a1/out1 p a0/out0 p97/in1 v cc 3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 av ss p60/an0 p61/an1 p62/an2 p63/an3 p64/an4 p65/an5 p66/an6 p67/an7 p80/irq 0 p81/irq 1 p82/irq 2 p83/irq 3 rst x0a x1a notes : ? i 2 c pin p76 and p77 are n-ch open drain pin (without p-ch) . ? p24 to p27, p30 to p37, p40 to p42, p70 to p74, p76 and p77 also used as 3 v/5 v i/f pin.
mb90980 series 7 pin descriptions (continued) pin no. pin name i/o circuit type* function 46 x0 a oscillator pin 47 x1 a oscillator pin 50 x0a a 32 khz oscillator pin 49 x1a a 32 khz oscillator pin 51 rst b reset input pin 3 to 6 p27 to p24 e (cmos/h) general purpose i/o port ppg3 to ppg0 ppg timer output pin 14 p30 e (cmos/h) general purpose i/o port ain0 8/16-bit up/down timer counter input pin (ch.0) 13 p31 e (cmos/h) general purpose i/o port bin0 8/16-bit up/down timer counter input pin (ch.0) 12 p32 e (cmos/h) general purpose i/o port zin0 8/16-bit up/down timer counter input pin (ch.0) 11 p33 e (cmos/h) general purpose i/o port ain1 8/16-bit up/down timer counter input pin (ch.1) 10 p34 e (cmos/h) general purpose i/o port bin1 8/16-bit up/down timer counter input pin (ch.1) 9 p35 e (cmos/h) general purpose i/o port zin1 8/16-bit up/down timer counter input pin (ch.1) 7, 8 p37, p36 e (cmos/h) general purpose i/o port pwc1, pwc0 pwc input pin 19 p40 g (cmos/h) general purpose i/o port sin2 simple serial i/o 2-input pin 18 p41 f (cmos) general purpose i/o port sot2 simple serial i/o 2-output pin 15 p42 g (cmos/h) general purpose i/o port sck2 simple serial i/o 2-clock i/o pin 60 to 63 p63 to p60 h (cmos) general purpose i/o port an3 to an0 analog input pin 56 to 59 p67 to p64 f (cmos) general purpose i/o port an7 to an4 analog input pin 26 p70 g (cmos/h) general purpose i/o port sin0 uart data input pin 25 p71 f (cmos) general purpose i/o port sot0 uart data output pin
mb90980 series 8 (continued) pin no. pin name i/o circuit type* function 24 p72 g (cmos/h) general purpose i/o port sck0 uart clock i/o pin 23 p73 g (cmos/h) general purpose i/o port tin0 16-bit reload timer event input pin 22 p74 f (cmos) general purpose i/o port tot0 16-bit reload timer output pin 21 p76 i (nmos/h) general purpose i/o port scl this pin functions as the i 2 c interface clock i/o pin. set port output to hi-z during the i 2 c interface operation. 20 p77 i (nmos/h) general purpose i/o port sda this pin functions as the i 2 c interface data i/o pin. set port output to hi-z during the i 2 c interface operation. 52 to 55 p83 to p80 e (cmos/h) general purpose i/o port irq3 to irq0 external interrupt input pin 39 to 42 p87 to p84 e (cmos/h) general purpose i/o port irq7 to irq4 external interrupt input pin 38 p90 e (cmos/h) general purpose i/o port sin1 simple serial i/o1-data input pin 37 p91 d (cmos) general purpose i/o port sot1 simple serial i/o-1 data output pin 36 p92 e (cmos/h) general purpose i/o port sck1 simple serial i/o-1 data i/o pin 35 p93 e (cmos/h) general purpose i/o port frck when using free-run timer, this pin functions as the external clock in- put pin. adtg when using a/d converter, this pin fuctions as the external trigger input pin. 34 p96 e (cmos/h) general purpose i/o port in0 input capture ch.0 trigger input pin 31 p97 e (cmos/h) general purpose i/o port in1 input capture ch.1 trigger input pin 27 to 30 pa3 to pa0 d (cmos) general purpose i/o port out3 to out0 output co mpare event output pin 1av cc ? a/d converter power supply pin 2avrh ? a/d converter external reference power supply pin 64 av ss ? a/d converter power supply pin 43 to 45 md0 to md2 j (cmos/h) operating mode selection input pins 32 v cc 3 ? 3.3 v 0.3 v power supply pins (v cc 3)
mb90980 series 9 (continued) * : refer to ? i/o circuit types? for i/o circuit types. pin no. pin name i/o circuit type* function 16 v cc 5 ? 3 v/5 v power supply pin. 5 v power supply pin when p24 to p27, p30 to p37, p40 to p42, p70 to p74, p76 an d p77 are used as 5 v i/f pins. usually, use v cc = v cc 3 = v cc 5 as a 3 v power supply (when the 3 v power supply is used alone) . 17, 33, 48 v ss ? power supply input pins (gnd)
mb90980 series 10 i/o circuit types (continued) type circuit remarks a ? oscillator feedback resistance x1, x0 : approx. 1 m ? x1a, x0a : approx. 10 m ? ? with standby control b hysteresis input with pull-up resistance c ? with input pull-up resistance control ? cmos level input/output d cmos level input/output e ? hysteresis input ? cmos level output x 1, x1a x 0, x0a hard/soft standby control signal hy s ctl cmos n-ch p-ch p-ch standby control signal cmos p-ch n-ch standby control signal cmos p-ch n-ch standby control signal
mb90980 series 11 (continued) type circuit remarks f ? cmos level input/output ? with open drain control g ? cmos level output ? hysteresis input ? with open drain control h ? cmos level input/output ? analog input i ? hysteresis input ? n-ch open drain output j ? cmos level input ? with high voltage control for flash testing hysteresis input p-ch n-ch cmos open drain control signal standby control signal p-ch n-ch open drain control signal standby control signal p-ch n-ch cmos analog input standby control signal digital output hys standby control signal control signal mode input diffusion resistance flash memory model hysteresis input mask rom model
mb90980 series 12 caution of using devices 1. maximum rated voltages (preventing latchup) in cmos ic devices, a condition known as la tchup may occur if vo ltages higher than v cc or lower than v ss are applied to input or output pins other than medium-or high-voltage pins, or if the voltage applied between v cc and v ss exceeds the rated voltage level. when latchup occurs, the power supply current increa ses rapidly causing the possibility of thermal damage to circuit elements. therefore it is necessary to ensure that maximum ratings are not exceeded in circuit operation. similarly, when turning the analog power supply on or off, it is necessary to ensure that the analog power supply voltages (av cc and avrh) and analog input voltages do not exceed the digital power supply (v cc ) . 2. treatment of unused pins leaving unused input pins unconnected can cause abnorma l operation or latchup, leading to permanent damage. unused input pins should always be pulled up or down through resistance of at least 2 k ? . any unused input/ output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. 3. notes on using external clock even when using an external clock signal, an oscilltion stabilization delay is applied after a power-on reset or when recovering from sub-clock or stop mode. when using an external clock, 25 mhz should be the upper frequency limit. the following figure shows a sample use of external clock signals. 4. treatment of power supply pins (v cc /v ss ) when multiple v cc pins or v ss pins are present, device design consid erations for prevention of latch-up and unwanted electromagnetic interference, abnormal storobe si gnal operation due to ground level rise, and confor- mity with total output current ratings require that all po wer supply pins must be externally connected to power supply or ground. consideration should be given to c onnecting power supply sources to the v cc pin or v ss pin of this device with as low impedane as possible. it is also recommended that a bypass capacitor of approximately 0.1 f be placed between the v cc and v ss lines as close to this device as possible. 5. crystal oscillator circuits noise around the high-speed oscillation pins (x0 and x1 ) and low-speed oscillation pins (x0a and x1a) may cause this device to operate abnormally. design the printed circuit board so t hat the crystal oscillator (or ceramic oscillator) and bypass capacitor to th e ground are located as close to the high-speed oscillation pins and low- speed oscillation pins as possible. also, design the pr inted circuit board to prevent the wiring from crossing another writing. it is highly recommended to provide a printed circuit b oard artwork surrounding the high-speed oscillation pins and low-speed oscillation pins with a gr ound area for stabilizing the operation. x 0 x 1 open
mb90980 series 13 6. notes on during operation of pll clock mode if the pll clock mode is selected, th e microcontroller attempt to be workin g with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. performance of this operation, however, cannot be guaranteed. 7. proper power-on/off sequence the a/d converter power (av cc , avrh) and analog input (an0 to an7) mu st be turned on after the digital power supply (v cc ) is turned on. the a/d converter power (av cc , avrh) and analog input (an0 to an7) must be shut off before the digital power supply (v cc ) is shut off. care should be taken that avrh does not exceed av cc . even when pins used as analog input pins are doubled as input ports, be sure that the input voltage does not exceed av cc . 8. treatment of power supply pins on models with a/d converters even when the a/d converters ar e not in use, be sure to ma ke the necessary connections av cc = avrh = v cc , and av ss = v ss . 9. precautions when turning the power supply on in order to prevent abnormal operation in the chip?s inte rnal step-down circuits, a voltage rise time during power- on of 50 s (0.2 v to 2.7 v) or greater should be assured. 10. supply voltage stabilization even within the operating range of v cc supply voltage, rapid voltage fluctuations may cause abnormal operation. as a standard for power supply voltage stability, it is recommended that the peak-to-peak v cc ripple voltage at commercial supply frequency (50 hz/60 hz) be 10 % or less of v cc , and that the transient voltage fluctuation be no more than 0.1 v/ms or less when the power supply is turned on or off. 11. notes on using power supply only the mb90980 series usually uses a 3 v power supply. by setting v cc 3 = 3 v power supply and v cc 5 = 5 v power supply, p24 to p27, p30 to p37, p40 to p42 and p70 to p74, p76, p77 can be intefaced as 5 v power supplies separately from the main 3 v power supply. note that the analog power supplies (such as av cc and av ss ) for the a/d converter can be us ed only as 3 v power supplies. 12. treatment of nc pins nc (internally connected) pins should always be left open. 13. writing to flash memory for serial writing to flash memory, al ways ensure that the operating voltage v cc is between 3.13 v and 3.6 v. for normal writing to flash memory, alwa ys ensure that the operating voltage v cc is between 3.0 v and 3.6 v.
mb90980 series 14 block diagram ram rom 8 2 x0, x1, rst x0a, x1a md2, md1, md0 sin0 sot0 sck0 sin1, sin2 sot1, sot 2 sck1, sck2 av cc avrh av ss adtg an0 to an7 2 p76, p77 2 p96, p97 pwc0 pwc1 clock control circuit cpu f 2 mc16lx series core interrupt controller ppg0, ppg1 ppg2, ppg3 8/16-bit ppg ain0, ain1 bin0, bin1 zin0, zin1 8/16-bit up/down counter in0, in1 out0, out1, out2, out3, input/output timer 16-bit input capture 2 channels 16-bit output compare 4 channels 16-bit free-run timer tin0 tot0 16-bit reload timer irq0 to irq7 8 external interrupt uart extended i/o serial interface 2 channels a/d converter ( 8/10-bit ) pwc 2 channels i/o port 4 p24 p27 to 8 p30 p37 to 3 p40 p42 to 8 p60 p67 to 5 p70 p74 to 8 p80 p87 to 4 p90 p93 to 4 pa 0 pa 3 to communication prescaler f 2 mc-16lx bus scl sda i 2 c interface 2 2 2 8 2 2 2 2 2 2 4 p40 to p42 ( 3) : with an open drain setting register i 2 c pin p77 and p76 are n-ch open drain pin (without p-ch) . note : in the above diagram, i/o ports share inte rnal function blocks and pins. however, when a set of pins is used with an internal module, it cannot also be used as an i/o port.
mb90980 series 15 memory map *1 : no memory cells from fc0000 h to fc7fff h and fe0000 h to fe7fff h . *2 : no memory cells from fe0000 h to feffff h . the upper part of the 00 bank is set up to mirror the image of ff bank rom, to enable efficient use of small model c compilers. because the lower 16-bit address of the ff bank and the lower 16-bit address of the 00 bank is th e same, enabling reference to tables in rom without the ?far? pointer declaration. for example, in accessing address 00c000 h it is actually the contents of rom at ffc000 h that are accessed. if the ms bit in the romm register is set to ?0?, t he rom area in the ff bank w ill exceed 48 kbytes and it is not possible to reflect the entire area in the image in the 00 bank. therefore the image from ff4000 h to ffffff h is reflected in the 00 bank and the area from ff0000 h to ff3fff h can be seen in the ff bank only. model address #1 address #2 address #3 mb90f983 fc0000 h * 1 004000 h or 008000 h , selected by the ms bit in the romm register 003100 h mb90982 fd0000 h * 2 002900 h ffffff h 0 10000 h 0 00100 h 0 000d0 h 0 00000 h ram f c0000 h register a ddress #1 a ddress #2 a ddress #3 rom area rom area, image of ff bank peripheral internal access no acces s single chip
mb90980 series 16 f 2 mc-16lx cpu programming model dedicated registers general purpose registers processor status ah al dpr pcb dtb usb ssb adb 8-bit 16-bit 32-bit usp ssp ps pc accumulator user stack pointer system stack pointer processor status program counter direct page register program counter bank register data bank register user stack bank register system stack bank register additional data bank register r1 r0 r3 r2 r5 r4 r7 r6 rw0 rw1 rw2 rw3 16-bit 000180 h + rp 10 h rw4 rw5 rw6 rw7 rl 0 rl 1 rl 2 rl 3 msb lsb ilm bit 15 bit 13 ps rp ccr bit 12 bit 8 bit 7 bit 0
mb90980 series 17 i/o map (continued) address abbreviated register name register name r/w resource name initial value 000000 h , 000001 h reserved area 000002 h pdr2 port 2 data register r/w port 2 xxxxxxxx b 000003 h pdr3 port 3 data register r/w port 3 xxxxxxxx b 000004 h pdr4 port 4 data register r/w port 4 xxxxxxxx b 000005 h reserved area 000006 h pdr6 port 6 data register r/w port 6 xxxxxxxx b 000007 h pdr7 port 7 data register r/w port 7 11xxxxxx b 000008 h pdr8 port 8 data register r/w port 8 xxxxxxxx b 000009 h pdr9 port 9 data register r/w port 9 xxxxxxxx b 00000a h pdra port a data register r/w port a - - - - xxxx b 00000b h uder up/down timer input enable register r/w up/down timer input control xx 0 0 0 0 0 0 b 00000c h enir interrupt/dtp enable register r/w dtp/external interrupts 0 0 0 0 0 0 0 0 b 00000d h eirr interrupt/dtp source register r/w xxxxxxxx b 00000e h elvr request level setting register r/w 0 0 0 0 0 0 0 0 b 00000f h request level setting register r/w 0 0 0 0 0 0 0 0 b 000010 h , 000011 h reserved area 000012 h ddr2 port 2 direction register r/w port 2 0 0 0 0 xxxx b 000013 h ddr3 port 3 direction register r/w port 3 0 0 0 0 0 0 0 0 b 000014 h ddr4 port 4 direction register r/w port 4 0 0 0 0 0 0 0 0 b 000015 h reserved area 000016 h ddr6 port 6 direction register r/w port 6 0 0 0 0 0 0 0 0 b 000017 h ddr7 port 7 direction register r/w port 7 xx 0 0 0 0 0 0 b 000018 h ddr8 port 8 direction register r/w port 8 0 0 0 0 0 0 0 0 b 000019 h ddr9 port 9 direction register r/w port 9 0 0 xx 0 0 0 0 b 00001a h ddra port a direction register r/w port a - - - - 0 0 0 0 b 00001b h odr4 port 4 output pin register r/w port 4 (open-drain control) xxxxx 0 0 0 b 00001c h , 00001d h reserved area 00001e h odr7 port 7 output pin register r/w port 7 (open-drain control) xxx 0 0 0 0 0 b 00001f h ader analog input enable register r/ w port 6, a/d 1 1 1 1 1 1 1 1 b 000020 h smr serial mode register r/w uart 0 0 0 0 0 x 0 0 b 000021 h scr serial control register w, r/w 0 0 0 0 0 1 0 0 b 000022 h sidr/sodr serial input/output register r/w xxxxxxxx b 000023 h ssr serial status register r, r/w 0 0 0 0 1 0 0 0 b 000024 h reserved area 000025 h cdcr communication prescaler control register r/w communication prescaler (uart) 0 0 - - 0 0 0 0 b
mb90980 series 18 (continued) address abbreviated register name register name r/w resource name initial value 000026 h smcs0 serial mode control status register 0 r, r/w sio1 (ch.0) - - - - 0 0 0 0 b 000027 h smcs0 serial mode control status register 0 r, r/w 0 0 0 0 0 0 1 0 b 000028 h sdr0 serial data register 0 r/w xxxxxxxx b 000029 h sdcr0 communication prescaler control register 0 r/w communication prescaler sio1 (ch.0) 0 - - - 0 0 0 0 b 00002a h smcs1 serial mode control status register 1 r, r/w sio2 (ch.1) - - - - 0 0 0 0 b 00002b h smcs1 serial mode control status register 1 r, r/w 0 0 0 0 0 0 1 0 b 00002c h sdr1 serial data register 1 r/w xxxxxxxx b 00002d h sdcr1 communication prescaler control register 1 r/w communication prescaler sio2 (ch.1) 0 - - - 0 0 0 0 b 00002e h prll0 reload register l (ch.0) r/w 8/16-bit ppg (ch.0 to ch.3) xxxxxxxx b 00002f h prlh0 reload register h (ch.0) r/w xxxxxxxx b 000030 h prll1 reload register l (ch.1) r/w xxxxxxxx b 000031 h prlh1 reload register h (ch.1) r/w xxxxxxxx b 000032 h prll2 reload register l (ch.2) r/w xxxxxxxx b 000033 h prlh2 reload register h (ch.2) r/w xxxxxxxx b 000034 h prll3 reload register l (ch.3) r/w xxxxxxxx b 000035 h prlh3 reload register h (ch.3) r/w xxxxxxxx b 000036 h to 000039 h reserved area 00003a h ppgc0 ppg0 operating mode control register r/w 8/16-bit ppg (ch.0 to ch.3) 0 x 0 0 0xx 1 b 00003b h ppgc1 ppg1 operating mode control register r/w 0 x 0 0 0 0 0 1 b 00003c h ppgc2 ppg2 operating mode control register r/w 0 x 0 0 0xx 1 b 00003d h ppgc3 ppg3 operating mode control register r/w 0 x 0 0 0 0 0 1 b 00003e h , 00003f h reserved area 000040 h ppg01 ppg0, ppg1 output control register r/w 8/16-bit ppg 0 0 0 0 0 0 0 0 b 000041 h reserved area 000042 h ppg23 ppg2, ppg3 output control register r/w 8/16-bit ppg 0 0 0 0 0 0 0 0 b 000043 h to 000045 h reserved area 000046 h adcs1 control status register r/w 8/10-bit a/d converter 0 0 0 0 0 0 0 0 b 000047 h adcs2 w, r/w 0 0 0 0 0 0 0 0 b 000048 h adcr1 data register r xxxxxxxx b 000049 h adcr2 w, r 0 0 0 0 0 xxx b
mb90980 series 19 (continued) address abbreviated register name register name r/w resource name initial value 00004a h occp0 output compare register (ch.0) lower digits r/w 16-bit i/o timer output compare (ch.0 to ch.3) 0 0 0 0 0 0 0 0 b 00004b h output compare register (ch.0) upper digits 0 0 0 0 0 0 0 0 b 00004c h occp1 output compare register (ch.1) lower digits r/w 0 0 0 0 0 0 0 0 b 00004d h output compare register (ch.1) upper digits 0 0 0 0 0 0 0 0 b 00004e h occp2 output compare register (ch.2) lower digits r/w 0 0 0 0 0 0 0 0 b 00004f h output compare register (ch.2) upper digits 0 0 0 0 0 0 0 0 b 000050 h occp3 output compare register (ch.3) lower digits r/w 0 0 0 0 0 0 0 0 b 000051 h output compare register (ch.3) upper digits 0 0 0 0 0 0 0 0 b 000052 h to 000055 h reserved area 000056 h ocs01 output compare control register (ch.0, ch.1) lower digits r/w 16-bit i/o timer output compare (ch.0 to ch.3) 0 0 0 0 - - 0 0 b 000057 h output compare control register (ch.0, ch.1) upper digits r/w - - - 0 0 0 0 0 b 000058 h ocs23 output compare control register (ch.2, ch.3) lower digits r/w 0 0 0 0 - - 0 0 b 000059 h output compare control register (ch.2, ch.3) upper digits r/w - - - 0 0 0 0 0 b 00005a h , 00005b h reserved area 00005c h ipcp0 input capture data register (ch.0) lower digits r 16-bit i/o timer input capture (ch.0, ch.1) xxxxxxxx b 00005d h input capture data register (ch.0) upper digits r xxxxxxxx b 00005e h ipcp1 input capture data register (ch.1) lower digits r xxxxxxxx b 00005f h input capture data register (ch.1) upper digits r xxxxxxxx b 000060 h ics01 input capture control status register r/w 0 0 0 0 0 0 0 0 b 000061 h reserved area 000062 h tcdt timer counter data register lower digits r/w 16-bit i/o timer free-run timer 0 0 0 0 0 0 0 0 b 000063 h tcdt timer counter data register upper digits r/w 0 0 0 0 0 0 0 0 b 000064 h tccs timer counter control status register r/w 0 0 0 0 0 0 0 0 b 000065 h tccs timer counter control status register r/w 0 - - 0 0 0 0 0 b 000066 h cpclr compare clear register lower digits r/w xxxxxxxx b 000067 h compare clear register upper digits xxxxxxxx b 000068 h udcr0 up/down count register (ch.0) r 8/16-bit up/ down counter/ timer 0 0 0 0 0 0 0 0 b 000069 h udcr1 up/down count register (ch.1) r 0 0 0 0 0 0 0 0 b 00006a h rcr0 reload/compare register (ch.0) w 0 0 0 0 0 0 0 0 b 00006b h rcr1 reload/compare register (ch.1) w 0 0 0 0 0 0 0 0 b 00006c h ccrl0 counter control register (ch.0) lower digits w, r/w 0 x 0 0 x 0 0 0 b 00006d h ccrh0 counter control register (ch.0) upper digits r/w 0 0 0 0 0 0 0 0 b
mb90980 series 20 (continued) address abbreviated register name register name r/w resource name initial value 00006e h reserved area 00006f h romm rom mirror function select register r/w rom mirroring function - - - - - - 0 1 b 000070 h ccrl1 counter control register (ch.1) lower digits r/w 8/16-bit up/down counter/timer 0 x 0 0 x 0 0 0 b 000071 h ccrh1 counter control register (ch.1) upper digits r/w - 0 0 0 0 0 0 0 b 000072 h csr0 counter status register (ch.0) r/w 0 0 0 0 0 0 0 0 b 000073 h reserved area 000074 h csr1 counter status register (ch.1) r, r/w 8/16-bit udc 0 0 0 0 0 0 0 0 b 000075 h reserved area 000076 h pwcsr0 pwc control/status register r, r/w pwc timer (ch.0) 0 0 0 0 0 0 0 0 b 000077 h 0 0 0 0 0 0 0 x b 000078 h pwcr0 pwc data buffer register r/w 0 0 0 0 0 0 0 0 b 000079 h 0 0 0 0 0 0 0 0 b 00007a h pwcsr1 pwc control/status register r, r/w pwc timer (ch. 1) 0 0 0 0 0 0 0 0 b 00007b h 0 0 0 0 0 0 0 x b 00007c h pwcr1 pwc data buffer register r/w 0 0 0 0 0 0 0 0 b 00007d h 0 0 0 0 0 0 0 0 b 00007e h to 000081 h reserved area 000082 h divr0 dividing ratio control regist er r/w pwc (ch.0) - - - - - - 0 0 b 000083 h reserved area 000084 h divr1 dividing ratio control regist er r/w pwc (ch.1) - - - - - - 0 0 b 000085 h to 000087 h reserved area 000088 h ibsr bus status register r i 2 c 0 0 0 0 0 0 0 0 b 000089 h ibcr bus control register r/w 0 0 0 0 0 0 0 0 b 00008a h iccr clock control register r/w - - 0 x x x x x b 00008b h iadr address register r/w - x x x x x x x b 00008c h idar data register r/w xxxxxxxx b 00008d h , 00008e h reserved area 00008f h to 00009b h disabled 00009c h dsrl dmac status register r/w dmac 0 0 0 0 0 0 0 0 b 00009d h dsrh dmac status register r/w dmac 0 0 0 0 0 0 0 0 b 00009e h pacsr program address detection control status resister r/w address match detection function 0 0 0 0 0 0 0 0 b 00009f h dirr dilayed interrupt source generator/ cancel register r/w delayed interruput generator module - - - - - - - 0 b
mb90980 series 21 (continued) address abbreviated register name register name r/w resource name initial value 0000a0 h lpmcr low-power consumption mode control register w, r/w low-power operation 0 0 0 1 1 0 0 0 b 0000a1 h ckscr clock select register r, r/w low-power operation 1 1 1 1 1 1 0 0 b 0000a2 h to 0000a7 h reserved area 0000a8 h wdtc watchdog timer control register r, w watchdog timer xxxxx 1 1 1 b 0000a9 h tbtc timebase timer control register w, r/w timebase timer 1 x x 0 0 1 0 0 b 0000aa h wtc watch timer control register r, r/w watch timer 1 0 0 0 1 0 0 0 b 0000ab h reserved area 0000ac h derl dmac enable register r/w dmac 0 0 0 0 0 0 0 0 b 0000ad h derh dmac enable register r/w dmac 0 0 0 0 0 0 0 0 b 0000ae h fmcs flash memory control status register w, r/w flash memory i/f 0 0 0 x 0 0 0 0 b 0000af h disabled 0000b0 h icr00 interrupt control register 00 w, r/w interrupt controller 0 0 0 0 0 1 1 1 b 0000b1 h icr01 interrupt control register 01 w, r/w 0 0 0 0 0 1 1 1 b 0000b2 h icr02 interrupt control register 02 w, r/w 0 0 0 0 0 1 1 1 b 0000b3 h icr03 interrupt control register 03 w, r/w 0 0 0 0 0 1 1 1 b 0000b4 h icr04 interrupt control register 04 w, r/w 0 0 0 0 0 1 1 1 b 0000b5 h icr05 interrupt control register 05 w, r/w 0 0 0 0 0 1 1 1 b 0000b6 h icr06 interrupt control register 06 w, r/w 0 0 0 0 0 1 1 1 b 0000b7 h icr07 interrupt control register 07 w, r/w 0 0 0 0 0 1 1 1 b 0000b8 h icr08 interrupt control register 08 w, r/w 0 0 0 0 0 1 1 1 b 0000b9 h icr09 interrupt control register 09 w, r/w 0 0 0 0 0 1 1 1 b 0000ba h icr10 interrupt control register 10 w, r/w 0 0 0 0 0 1 1 1 b 0000bb h icr11 interrupt control register 11 w, r/w 0 0 0 0 0 1 1 1 b 0000bc h icr12 interrupt control register 12 w, r/w 0 0 0 0 0 1 1 1 b 0000bd h icr13 interrupt control register 13 w, r/w 0 0 0 0 0 1 1 1 b 0000be h icr14 interrupt control register 14 w, r/w 0 0 0 0 0 1 1 1 b 0000bf h icr15 interrupt control register 15 w, r/w 0 0 0 0 0 1 1 1 b 0000c0 h to 0000c9 h reserved area 0000ca h tmcsr timer control status register r/w 16-bit reload timer 0 0 0 0 0 0 0 0 b 0000cb h - - - - 0 0 0 0 b 0000cc h tmr/tmrlr 16-bit timer register/ 16-bit reload register r/w xxxxxxxx b 0000cd h 0000ce h reserved area
mb90980 series 22 (continued) notes : ? descriptions for r/w ? descriptions for initial value address abbreviated register name register name r/w resource name initial value 0000cf h pllos pll output select register w low-power operation - - - - - - 0 0 b 0000d0 h to 0000ff h external area 000100 h to 00000# h ram area 001ff0 h padr0 program address detection resister 0 (low order address) r/w address match detection function xxxxxxxx b 001ff1 h program address detection resister 0 (middle order address) 001ff2 h program address detection resister 0 (high order address) 001ff3 h padr1 program address detection resister 1 (low order address) r/w address match detection function xxxxxxxx b 001ff4 h program address detection resister 1 (middle order address) 001ff5 h program address detection resister 1 (high order address) r/w : enabled to read and write r : read only w : write only 0 : the initila value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined. - : this bit is not used.
mb90980 series 23 interrupt sources, interrupt vectors, and interrupt control registers (continued) interrupt source clear of ei 2 os dmac cnannel number interrupt vector interrupt control register number address number address reset ? #08 ffffdc h ?? int9 instruction ? #09 ffffd8 h ?? exception ? #10 ffffd4 h ?? int0 (irq0) 0 #11 ffffd0 h icr00 0000b0 h int1 (irq1) #12 ffffcc h int2 (irq2) #13 ffffc8 h icr01 0000b1 h int3 (irq3) #14 ffffc4 h int4 (irq4) #15 ffffc0 h icr02 0000b2 h int5 (irq5) #16 ffffbc h int6 (irq6) #17 ffffb8 h icr03 0000b3 h int7 (irq7) #18 ffffb4 h pwc1 #19 ffffb0 h icr04 0000b4 h ??? #20 ffffac h pwc0 1 #21 ffffa8 h icr05 0000b5 h ppg0/ppg1 counter borrow 2 #22 ffffa4 h ppg2/ppg3 counter borrow 3 #23 ffffa0 h icr06 0000b6 h ??? #24 ffff9c h 8/16-bit up/down counter/ timer (ch.0, ch.1) compare/ underflow/overflow/inversion #25 ffff98 h icr07 0000b7 h input capture (ch.0) load 5 #26 ffff94 h input capture (ch.1) load 6 #27 ffff90 h icr08 0000b8 h output compare (ch.0) match 8 #28 ffff8c h output compare (ch.1) match 9 #29 ffff88 h icr09 0000b9 h output compare (ch.2) match 10 #30 ffff84 h output compare (ch.3) match #31 ffff80 h icr10 0000ba h ??? #32 ffff7c h ??? #33 ffff78 h icr11 0000bb h uart sending completed 11 #34 ffff74 h 16-bit free run timer overflow, 16-bit reload timer underflow* 2 12 #35 ffff70 h icr12 0000bc h uart receiving compleated 7 #36 ffff6c h sio1 (ch.0) 13 #37 ffff68 h icr13 0000bd h sio2 (ch.1) 14 #38 ffff64 h
mb90980 series 24 (continued) : interrupt request flag is not cl eared by the interrupt clear signal. : interrupt request flag is clea red by the interrupt clear signal. : interrupt request flag is cleared by the interrupt clear signal (stop request present) . *1 : caution : the flash write/erase, timebase time r, and watch timer cannot be used at the same time. *2 : when the 16-bit reload timer underflow interr upt is changed from en able (tmcsr : inte = 1) to disable (tmcsr : inte = 0) , disable the interrupt in the interrupt control register (icr12 : il2 to il0 : 111 b ) , then set the inte bit to 0. note : if there are two interrupt sources for the same inte rrupt number, the interrupt r equest flags of both resources are cleared by the ei 2 os/ dmac. therefore if either of the two sources uses the ei 2 os/ dmac function, the other interrupt function cannot be used. the interrupt request enable bit for the resource that does not use the ei 2 os/ dmac function should be set to ?0? and the inte rrupt function should be handled by software polling. interrupt source clear of ei 2 os dmac channel number interrupt vector interrupt control register number address number address i 2 c interface #39 ffff60 h icr14 0000be h 8/10-bit a/d converter 15 #40 ffff5c h flash write/erase, timebase timer,watch timer * 1 #41 ffff58 h icr15 0000bf h delay interrupt generator module #42 ffff54 h
mb90980 series 25 electrical characteristics 1. absolute maximum ratings *1 : this parameter is based on v ss = av ss = 0.0 v. *2 : av cc and avrh must not exceed v cc . also, avrh must not exceed av cc . *3 : v 1 and v 0 must not exceed v cc + 0.3 v. however, if the maximum curre nt to/from input is limited by some means with external components, the i clamp rating supersedes the v i rating. *4 : maximum output current is defined as the peak value for one of the corresponding pins. *5 : average output current is defined as the average current flow in a 100 ms interval at one of the corresponding pins. *6 : average total output current is defined as the average cu rrent flow in a 100 ms interval at all corresponding pins. *7 : ? applicable to pins : p24 to p2 7, p30 to p37, p40 to p42, p60 to p67, p70 to p74, p76, p77, p80 to p87, p90 to p93, p96, p97, pa0 to pa3 ? use within recommended operating conditions. ? use at dc voltage (current) . ? the + b signal should always be applied wi th a limiting resistance placed between the + b signal and the microcontroller. ? the value of the limiting resistan ce should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated valu es, either instantaneously or for prolonged periods. parameter symbol rating unit remarks min max power supply voltage* 1 v cc 3v ss ? 0.3 v ss + 4.0 v v cc 5v ss ? 0.3 v ss + 7.0 v av cc v ss ? 0.3 v ss + 4.0 v *2 avrh v ss ? 0.3 v ss + 4.0 v input voltage* 1 v i v ss ? 0.3 v ss + 4.0 v *3 v ss ? 0.3 v ss + 7.0 v *3, *8, *9 output volatage* 1 v o v ss ? 0.3 v ss + 4.0 v *3 v ss ? 0.3 v ss + 7.0 v *3, *8, *9 maximum clamp current i clamp ? 2.0 + 2.0 ma *7 total maximum clamp current ? i clamp ?? 20 ma *7 ?l? level maximum output current i ol ? 10 ma *4 ?l? level average output current i olav ? 3ma*5 ?l? level maximum total output current i ol ? 60 ma ?l? level total average output current i olav ? 30 ma *6 ?h? level maximum output current i oh ?? 10 ma *4 ?h? level average output current i ohav ?? 3ma*5 ?h? level maximum total output current i oh ?? 60 ma ?h? level total average output current i ohav ?? 30 ma *6 power consumption p d ? 320 mw operating temperature t a ? 40 + 85 c storage temperature tstg ? 55 + 150 c
mb90980 series 26 ? note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective di ode and increase the potential at the v cc pin, and this may affect other devices. ? note that if a + b signal is input when the microcontroller current is off (not fixed at 0 v) , the power supply is provided from the pins, so t hat incomplete operation may result. ? note that if the + b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be suff icient to operate the power-on reset. ? care must be taken not to leave the + b input pin open. ? note that analog system input/output pins other than the a/d input pins (lcd drive pins, comparator input pins, etc.) cannot accept + b signal input. ? sample recommended circuits: *8 : p24 to p27, p30 to p37, p40 to p42, p70 to p74, p76, p77 pins can be used as 5 v i/f pin on applied 5 v to v cc 5 pin. p76 and p77 is n-ch open drain pin. *9 : as for p76 and p77 (n-ch open drain pi n) , even if using at 3 v simplicity (v cc 3 = v cc 5) , the ratings are applied. warning: semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. p-ch n-ch v cc r protective diode limiting resistance + b input (0 v to 16 v) input/output equivalent circuits
mb90980 series 27 2. recommended operating conditions (v ss = av ss = 0.0 v) * : p24 to p27, p30 to p37, p40 to p4 2, p70 to p74, p76, p77 pins can be used as 5 v i/f pin on applied 5 v to v cc 5 pin. warning: the recommended operating conditions are require d in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min max supply voltage v cc 3 2.7 3.6 v during normal operation 1.8 3.6 v to maintain ram state in stop mode v cc 5 2.7 5.5 v during normal operation* 1.8 5.5 v to maintain ram state in stop mode* ?h? level input voltage v ih 0.7 v cc v cc + 0.3 v all pins other than v ih2 , v ihs , v ihm and v ihx v ih2 0.7 v cc v ss + 5.8 v p76, p77 pins (n-ch open drain pins) v ihs 0.8 v cc v cc + 0.3 v hysteresis input pins v ihm v cc ? 0.3 v cc + 0.3 v md pin input v ihx 0.8 v cc v cc + 0.3 v x0a pin, x1a pin ?l? level input voltage v il v ss ? 0.3 0.3 v cc v all pins other than v ils , v ilm and v ihx v ils v ss ? 0.3 0.2 v cc v hysteresis input pins v ilm v ss ? 0.3 v ss + 0.3 v md pin input v ilx v ss ? 0.3 0.1 v x0a pin, x1a pin operating temperature t a ? 40 + 85 c
mb90980 series 28 3. dc characteristics (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) notes : ? pins p40 to p42, p70 to p74, p76, and p77 are n- ch open drain pins with control, which are usually used as cmos. ? p76 and p77 are open drain pins without p-ch. ? for use as a single 3 v power supply products, set v cc = v cc 3 = v cc 5. ? when the device is used with dual power supplies, p24 to p27, p30 to p37, p40 to p42, p70 to p74, p76 and p77 serve as 5 v pins while t he other pins serve as 3 v i/o pins. parameter symbol pin name condition value unit remarks min typ max ?h? level output voltage v oh all output pins v cc = 2.7 v, i oh = ? 1.6 ma v cc 3 ? 0.3 ?? v v cc = 4.5 v, i oh = ? 4.0 ma v cc 5 ? 0.5 ?? v at using 5 v power supply ?l? level output voltage v ol all output pins v cc = 2.7 v, i ol = 2.0 ma ?? 0.4 v v cc = 4.5 v, i oh = 4.0 ma ?? 0.4 v at using 5 v power supply input leakage current i il all input pins v cc = 3.3 v, v ss < v i < v cc ? 10 ?+ 10 a pull-up resistance r pull ? v cc = 3.0 v, at t a = + 25 c 20 53 200 k ? open drain output current i leak p40 to p42, p70 to p74, p76, p77 ?? 0.1 10 a power supply current i cc ? at v cc = 3.3 v, internal 25 mhz operation, normal operation ? 45 60 ma at v cc = 3.3 v, internal 25 mhz operation, flash programming ? 55 70 ma i ccs ? at v cc = 3.3 v, internal 25 mhz operation, sleep mode ? 17 35 ma i ccl ? at v cc = 3.3 v, external 32 khz, internal 8 khz operation, sub clock operation (t a = + 25 c) ? 15 140 a i cct ? at v cc = 3.3 v, external 32 khz, internal 8 khz operation, watch mode (t a = + 25 c) ? 1.8 40 a i cch ? t a = + 25 c, stop mode, at v cc = 3.3 v ? 0.8 40 a input capacitance c in other than av cc , av ss , v cc , v ss ?? 515pf
mb90980 series 29 4. ac characteristics (1) clock timing (v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : be careful of the operating voltage. *2 : duty raito should be 50 % 3 % . parameter sym- bol pin name condi- tion value unit remarks min typ max clock frequency f ch x0, x1 ? 3 ? 25 mhz external crystal oscillator ? 3 ? 50 external clock input ? 4 ? 25 1 multiplied pll ? 3 ? 12.5 2 multiplied pll ? 3 ? 6.66 3 multiplied pll ? 3 ? 6.25 4 multiplied pll ? 3 ? 4.16 6 multiplied pll ? 3 ? 3.12 8 multiplied pll f cl x0a, x1a ?? 32.768 ? khz clock cycle time t c x0, x1 ? 20 ? 333 ns *1 t cl x0a, x1a ?? 30.5 ? s input clock pulse width p wh p wl x0 ? 5 ?? ns p wlh p wll x0a ?? 15.2 ? s*2 input clock rise, fall time t cr t cf x0 ??? 5 ns with external clock internal operating clock frequency f cp ?? 1.5 ? 25 mhz *1 f cpl ??? 8.192 ? khz internal operating clock cycle time t cp ?? 40.0 ? 666 ns *1 t cpl ??? 122.1 ? s
mb90980 series 30 x0, x1 clock timing x 0 t c t cf t cr 0.8 v c c 0.2 v c c p wh p wl x0a, x1a clock timing x 0a t cl t cf t cr 0.8 v c c 0.1 v p wlh p wll
mb90980 series 31 3.6 2.7 3.0 4 1.5 16 25 16 12 25 8 4 34 8 12.5 16 25 20 32 50 20 6 1 .5 9 18 24 5 6 10 40 range of warranted pll operation normal operating range supply voltage v cc (v) internal clock f cp (mhz) internal operating clock freq uency vs. power supply voltage base oscillator frequency vs. inte rnal operating clock frequency base oscillator clock f ch (mhz) internal clock f cp (mhz) range of warranted pll operation notes: ? only at 1 multiplied pll, use with more than f cp = 4 mhz. ? for a/d operating frequency, refer to ?5. a/d converter electrical characteristics?. no multiplied *1 : in setting as 1, 2, 3 and 4 multiplied pll, when the internal clock is used at 20 mhz < f cp 25 mhz, set the pllos register to ?div2 bit = 1? and ?pll2 bit = 1?. [example] when using the base oscillator fr equency of 24 mhz at 1 multiplied pll : ckscr register : cs1 bit = ?0?, cs0 bit = ?0? pllos register : div2 bit = ?1?, pll2 bit = ?1 ? [example] when using the base oscillator fr equency of 6 mhz at 3 multiplied pll : ckscr register : cs1 bit = ?1?, cs0 bit = ?0? pllos register : div2 bit = ?1?, pll2 bit = ?1 ? *2 : in setting as 2 and 4 multiplied pll, when the internal clock is used at 20 mhz < f cp 25 mhz, the following setting is also enabled. 2 multiplied pll : ckscr register : cs1 bit = ?0?, cs0 bit = ?0? pllos register : div2 bit = ?0?, pll2 bit = ?1? 4 multiplied pll : ckscr register : cs1 bit = ?0?, cs0 bit = ?1? pllos register : div2 bit = ?0?, pll2 bit = ?1? *3 : when using in setting as 6 and 8 multipli ed pll, set the pllos register to ?div2 bit = 0? and ?pll2 bit = 1? . [example] when using the base oscillator fr equency of 4 mhz at 6 multiplied pll : ckscr register : cs1 bit = ?1?, cs0 bit = ?0? pllos register : div2 bit = ?0?, pll2 bit = ?1 ? [example] when using the base oscillator fr equency of 3 mhz at 8 multiplied pll : ckscr register : cs1 bit = ?1?, cs0 bit = ?1? pllos register : div2 bit = ?0?, pll2 bit = ?1 ? 1* 1 2* 1, * 2 3* 1 4 * 1, * 2 6* 3 8* 3
mb90980 series 32 ac standards are set at the following measurement voltage values. 0 .8 v cc 0 .2 v cc 2.4 v 0.8 v 0 .7 v cc 0 .3 v cc input signal waveform hysteresis input pins output signal waveform output pins pins other than hysteresis input/md input
mb90980 series 33 (2) reset input standards (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : t cp is internal operating clock cycle time. refer to ? (1) clock timing?. *2 : oscillator oscillation time is the time to 90 % of amplitude. for a crystal oscillato r this is on the order of several milliseconds to tens of milliseconds. for a far/ceramic oscillator, this is several hundred microseconds to several milliseconds. for an external clock signal the value is 0 ms. parameter symbol pin name condi- tions value unit remarks min max reset input time t rstl rst ? 16 t cp * 1 ? ns normal operation oscillator oscillation time* 2 + 4 t cp * 1 ? ms stop mode r st x0 4 t cp t rstl 0.2 vcc 0.2 vcc in stop mode internal operating clock internal reset oscillator oscillation time oscillator stabil ization wait time instruction execution 90 % of amplitude
mb90980 series 34 (3) power-on reset standards (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) * : power rise time requires v cc < 0.2 v. notes: ? the above standards are for the application of a power-on reset. ? within the device, the power-on reset should be ap plied by switching the power supply off and on again. parameter symbol pin name conditions value unit remarks min max power rise time t r v cc ? ? 30 ms * power down time t off v cc 1 ? ms in repeated operation v cc v cc v ss t r t off 2.7 v 0.2 v 0.2 v 0.2 v rapid fluctuations in power supply volt age may trigger a power-on reset in some cases. as shown below, when changing supp ly voltage during operation, it is recommended that voltage c hanges be suppressed and a smooth restart be applied. the slope of voltage increase should be kept within 50 mv/ms. ram data maintenance main power supply voltage sub power supply voltage
mb90980 series 35 (4) uart timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : c l is the load capacitance ap plied to pins for testing. *2 : t cp is internal operating clock cycle time. refer to ? (1) clock timing?. note : ac ratings are for clk synchronized mode. parameter symbol pin conditions value unit remarks min max serial clock cycle time t scyc ? internal shift clock mode output pins : c l * 1 = 80 pf + 1 ttl 8 t cp * 2 ? ns sck sot delay time t slov ? ? 80 + 80 ns ? 120 + 120 ns f cp = 8 mhz valid sin sck t ivsh ? 100 ? ns 200 ? ns f cp = 8 mhz sck valid sin hold time t shix ? t cp * 2 ? ns serial clock ?h? pulse width t shsl ? external shift clock mode output pins : c l * 1 = 80 pf + 1 ttl 4 t cp * 2 ? ns serial clock ?l? pulse width t slsh ? 4 t cp * 2 ? ns sck sot delay time t slov ? ? 150 ns ? 200 ns f cp = 8 mhz valid sin sck t ivsh ? 60 ? ns 120 ? ns f cp = 8 mhz sck valid sin hold time t shix ? 60 ? ns 120 ? ns f cp = 8 mhz
mb90980 series 36 internal shift clock mode external shift clock mode s ck s ot s in t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc s ck s ot s in t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc
mb90980 series 37 (5) extended i/o se rial interface timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : c l is the load capacitance ap plied to pins for testing. *2 : t cp is internal operating clock cycle time. refer to ? (1) clock timing?. notes : ? ac ratings are for clk synchronized mode. ? values on this table are target values. parameter symbol pin name conditions value unit remarks min max serial clock cycle time t scyc ? internal shift clock mode output pins : c l * 1 = 80 pf + 1 ttl 8 t cp * 2 ? ns sck sot delay time t slov ? ? 80 + 80 ns ? 120 + 120 ns f cp = 8 mhz valid sin sck t ivsh ? 100 ? ns 200 ? ns f cp = 8 mhz sck valid sin hold time t shix ? t cp * 2 ? ns serial clock ?h? pulse width t shsl ? external shift clock mode output pins : c l * 1 = 80 pf + 1 ttl 4 t cp * 2 ? ns serial clock ?l? pulse width t slsh ? 4 t cp * 2 ? ns sck sot delay time t slov ? ? 150 ns ? 200 ns f cp = 8 mhz valid sin sck t ivsh ? 60 ? ns 120 ? ns f cp = 8 mhz sck valid sin hold time t shix ? 60 ? ns 120 ? ns f cp = 8 mhz
mb90980 series 38 internal shift clock mode external shift clock mode s ck s ot s in t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc s ck s ot s in t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc
mb90980 series 39 (6) timer input timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) * : t cp is internal operating clock cycle time. refer to ? (1) clock timing?. (7) timer output timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh t tiwl tin0, in0, in1, pwc0, pwc1 ? 4 t cp * ? ns parameter sym- bol pin name conditions value unit remarks min max clk tout change time ppg0 to ppg3 change time out0 to out3 change time t to tot0, ppg0 to ppg3, out0 to out3 load conditions 80 pf 30 ? ns 0.8 v cc t in0 i n0, in1 p wc0, pwc1 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl 0.7 v cc c lk t out 0.3 v cc 0.7 v cc t to p pg0 to ppg3 o ut0 to out3
mb90980 series 40 (8) i 2 c timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : f cp is internal operation clock fre quency. refer to ? (1) clock timing?. *2 : r,c : pull-up resistor and lo ad capacitor of the scl and sda lines. *3 : the maximum t hddat only has to be met if the device does not stretch the ?l? width (t low ) of the scl signal. note : v cc = v cc 3 = v cc 5 parameter symbol condition standard-mode unit min max scl clock frequency f scl when power supply voltage of external pull-up resistance is 5.5 v r = 1.3 k ? , c = 50 pf* 2 when power supply voltage of external pull-up resistance is 3.6 v r = 1.6 k ? , c = 50 pf* 2 0 100 khz hold time (repeated) start condition sda scl t hdsta 4.0 ? s ?l? width of the scl clock t low 4.7 ? s ?h? width of the scl clock t high 4.0 ? s set-up time (repeated) start condition scl sda t susta 4.7 ? s data hold time scl sda t hddat 0 3.45* 3 s data set-up time sda scl t sudat when power supply voltage of external pull-up resistance is 5.5 v f cp * 1 20 mhz, r = 1.3 k ? , c = 50 pf* 2 when power supply voltage of external pull-up resistance is 3.6 v f cp * 1 20 mhz, r = 1.6 k ? , c = 50 pf* 2 250 ? ns when power supply voltage of external pull-up resistance is 5.5 v f cp * 1 > 20 mhz, r = 1.3 k ? , c = 50 pf* 2 when power supply voltage of external pull-up resistance is 3.6 v f cp * 1 > 20 mhz, r = 1.6 k ? , c = 50 pf* 2 200 ? ns set-up time for stop condition scl sda t susto when power supply voltage of external pull-up resistance is 5.5 v r = 1.3 k ? , c = 50 pf* 2 when power supply voltage of external pull-up resistance is 3.6 v r = 1.6 k ? , c = 50 pf* 2 4.0 ? s bus free time between a stop and start condition t bus 4.7 ? s sda scl t low t hddat t high t sudat t hdsta t susta t hdsta t susto t bus
mb90980 series 41 (9) trigger input timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) * : t cp is internal operating clock cycle time. refer to ? (1) clock timing?. (10) up-down counter timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) * : t cp is internal operating clock cycle time. refer to ? (1) clock timing?. parameter symbol pin name condi- tions value unit remarks min max input pulse width t trgh , t trgl adtg, irq0 to irq7 ? 5 t cp * ? ns normal operation 1 ? s stop mode parameter symbol pin name conditions value unit remarks min max ain input ?h? pulse width t ahl ain0, ain1, bin0, bin1 load conditions 80 pf 8 t cp * ? ns ain input ?l? pulse width t all 8 t cp * ? ns bin input ?h? pulse width t bhl 8 t cp * ? ns bin input ?l? pulse width t bll 8 t cp * ? ns ain bin rise time t aubu 4 t cp * ? ns bin ain fall time t buad 4 t cp * ? ns ain bin rise time t adbd 4 t cp * ? ns bin ain rise time t bdau 4 t cp * ? ns bin ain rise time t buau 4 t cp * ? ns ain bin fall time t aubd 4 t cp * ? ns bin ain rise time t bdad 4 t cp * ? ns ain bin rise time t adbu 4 t cp * ? ns zin input ?h? pulse width t zhl zin0, zin1 4 t cp * ? ns zin input ?l? pulse width t zll 4 t cp * ? ns 0.8 v cc i rq0 to irq7 a dtg 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl
mb90980 series 42 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.2 v cc t all t bll t bhl t ahl t aubu t buad t adbd t bdau a in b in 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.2 v cc t buau t aubd t zhl t zll t bdad t adbu b in a in z in
mb90980 series 43 5. a/d converter electrical characteristics (v cc = av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, 2.7 v avrh, t a = ? 40 c to + 85 c) *1 : at machine clock frequency of 25 mhz. *2 : cpu stop mode current when a/ d converter is not operating (at v cc = av cc = avrh = 3.0 v) . parameter symbol pin name value unit remarks min typ max resolution ?? ? ? 10 bit total error ?? ? ? 3.0 lsb non-linear error ?? ? ? 2.5 lsb differential linearity error ?? ? ? 1.9 lsb zero transition voltage v ot an0 to an7 av ss ? 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb mv full scale transition voltage v fst an0 to an7 avrh ? 3.5 lsb avrh ? 1.5 lsb avrh + 0.5 lsb mv conversion time ?? 3.68 * 1 ?? s analog port input current i ain an0 to an7 ? 0.1 10 a analog input voltage v ain an0 to an7 av ss ? avrh v reference voltage ? avrh av ss + 2.2 ? av cc v power supply current i a av cc ? 1.4 3.5 ma i ah av cc ?? 5 * 2 a reference voltage supply current i r avrh ? 94 150 a i rh avrh ?? 5 * 2 a offset between channels ? an0 to an7 ?? 4lsb
mb90980 series 44 ? about the external impedance of th e analog input and its sampling time a/d converter with sample and hold circuit. if the exte rnal impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting a/d conversion precision. to satisfy the a/d conversion precision standard, co nsider the relationship between the external impedance and minimum sampling time and either adjust the resi stor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. if the sampling time cannot be suffici ent, connect a capacitor of about 0.1 f to the analog input pin. ? about errors as |avrh ? av ss | becomes smaller, values of relative errors grow larger. note : concerning sampling time, and compare time when 3.6 v av cc 2.7 v, then sampling time : 1.92 s, compare time : 1.1 s settings should ensure that actual values do not go be low these values due to operating frequency changes. r c during sampling : on analog input comparator note: the values are reference values. analog input circuit model rc mb90982 2.5 k ? (max) 31.0 pf (max) mb90f983 1.9 k ? (max) 25.0 pf (max) mb90f983 mb90982 100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 mb90f983 mb90982 20 18 16 14 12 10 8 6 4 2 0 0123456 8 7 (external impedance = 0 k ? to 100 k ? ) (external impedance = 0 k ? to 100 k ? ) minimum sampling time [ s] minimum sampling time [ s] external impedance [k ? ] external impedance [k ? ] ? the relationship between external impedance and minimum sampling time
mb90980 series 45 flash memory program/erase characteristics * : the value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into normalized value at + 85 c) . use of the x0/x1, x0a/x1a pins sample use with external clock input parameter conditions value unit remarks min typ max sector erase time t a = + 25 c, v cc = 3.0 v ? 115s excludes 00 h programming prior erasure chip erase time ? 7 ? s excludes 00 h programming prior erasure word (16-bit) programming time ? 16 3600 s excludes system-level overhead program/erase cycle ? 10000 ?? cycle flash memory data hold time average t a = + 85 c 10 ?? year * x1 c3 c 4 c2 c1 x0 x0a x1a when used with a crystal oscillator pull-up resistance 1 damping resistance 1 damping resistance 2 internal damping resistance 0 in normal use : internal damping resistance 1 : typ 600 k ? consult with the os cillator manufacturer. pull-up resistance 1, damping resistance 1, 2, c1 to c4 x0 x1 open mb90980 series
mb90980 series 46 ordering information model package remarks mb90f983 mb90982 64-pin plastic lqfp (fpt-64p-m03)
mb90980 series 47 package dimensions 64-pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 10.0 10.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max weight 0. 3 2g code (reference) p-lfqfp64-10 10-0.50 64-pin pl as tic lqfp (fpt-64p-m0 3 ) (fpt-64p-m0 3 ) lead no. det a il s of "a" p a rt 0.25(.010) ( s t a nd off) (.004.004) 0.100.10 (.024.006) 0.600.15 (.020.00 8 ) 0.500.20 1.50 +0.20 ?0.10 +.00 8 ?.004 .059 0 ? ~ 8 ? "a" 0.0 8 (.00 3 ) (.006.002) 0.1450.055 0.0 8 (.00 3 ) m (.00 8 .002) 0.200.05 0.50(.020) 12.000.20(.472.00 8 ) s q 10.000.10(. 3 94.004) s q index 49 64 33 4 8 17 3 2 16 1 200 3 fujit s u limited f64009 s -c-5- 8 c (mo u nting height) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder.
mb90980 series f0604 the information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/mic roelectronics/product/micom/support/index.html fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. edited business promotion dept.

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